Phase lock loops are currently in use in many control areas from speed and angular rate control mechanisms to communication systems which employ frequency tracking methods for FM reception. In all phase lock loop systems, a signal from a variable frequency oscillator is compared with a cyclical incoming signal in a phase detector. The output of the phase detector, which is nominally a voltage proportional to the phase angle between the incoming and feedback frequencies is amplified and applied as a command to a voltage controlled oscillator (VCO). The frequency of the VCO is normally higher than the incoming frequency, and is normally down counted by a factor of N to the nominal frequency range of the incoming signal and is applied as a reference to a mixer. In actuality, since the output of the counter, the VCO and the operation of the mixer tend to be rich in harmonics, the mixer output will contain harmonics of the incoming frequency in addition to the error signal. The harmonic signals are removed by a low pass filter.
Phase lock loops present design difficulties in three areas, namely, "pull-in", "tracking rate" and "hold in range." Of these characteristics, the hold in range is most straightforward. It is determined by the range of the oscillator and the integrator output and is a readily controlled design parameter. Tracking rate is limited by the bandwidth of the phase lock loop itself and, with conventional techniques, it may be impossible to achieve a desired frequency tracking rate at a given operating frequency and loop bandwidth. "Pull-in" presents the most severe problem in phase-lock loop design. In the event that the incoming and reference frequencies differ by an amount greater than the frequency change represented by a phase error of .pi./2 radians, the error signal from the phase detector is not large enough to bring the VCO to synchronize with the incoming frequency. Therefor, the frequency difference will remain and a cyclical output from the phase detector results, having virtually no DC level to build up a signal on the integrator.